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James Glenn-Anderson

James Glenn-Anderson, Phd
James Anderson holds MSEE and PhD degrees from University of Minnesota. He has many years experience in scientific supercomputing starting with doctoral research using the Cray Y-MP/4 subsequently leading to a series of lead hardware architecture design/R&D positions at Quicksilver Technology, Chameleon Systems, and Xilinx Laboratories. His list of accomplishments include invention of the Multi-Processor Array single chip supercomputer (Xilinx), co-development of the first partially reconfigurable desktop dataflow supercomputer (DRC Computer), and invention of the FPGA-based Spatiotemporal Dataflow Processor (SSI). He is also Founder and Senior Research Scientist for the Mathematical Systems Theory Research Institute (MSTRI).


Memory Access-based Multi-Processor Array
US 7,831,801 November 9, 2010

Multiprocessor System with Cache Controlled Scatter-Gather Operations
US 7,620,780 November 17, 2009

Generic DMA IP Core Interface for FPGA Platform Design
US 7,536,669 May 19, 2009

Method and System for Partially Reconfigurable Switch
US 7,521,961 April 21, 2009

Hardware Stack Structure Using Programmable Logic
US 7,500,060 March 3, 2009

Circuit for and Method of Enabling Partial Reconfiguration of a Device having Programmable Logic
US 7,477,072 January 13, 2009

Writeable Shift Register Lookup Table in FPGA with SRAM Memory Cells in Lookup Table Reprogrammed by Writing after Initial Configuration
US 7,463,056 December 9, 2008

Power Amplifier Predistortion Methods and Apparatus using Envelope and Phase Detector
US 8,224,266 July 17, 2012


An Optimal Spatiotemporal Noise Filter for NI/OCT Imaging
J. Anderson, Y. Yu 2019 Asilomar Conference on Signals, Systems, and Computers

A Reduced Complexity SFSR Upscaler for Embedded Far-Infrared Streaming Video
J. Anderson 2018 Asilomar Conference on Signals, Systems, and Computers

Optimization of Photometric Warp SFSR Noise Transfer in Thermal Imaging Upscalers
J. Anderson 2018 Asilomar Conference on Signals, Systems, and Computers

Photometric Warp-based SFSR with Application to Infrared Image Processing
J. Anderson 2017 Asilomar Conference on Signals, Systems, and Computers

Dynamically Reconfigurable Multi-Processor Arrays
J. Anderson, 2014 Asilomar Conference on Signals, Systems, and Computers

Modular Dynamic Reconfiguration in Virtex FPGAs
P. Sedcole, J. Anderson, et al. IEE Proceedings – Computers and Digital Techniques 153(3): 157-164 2006

Evaluation of '1/f' Spectra in 'n+-p' Junctions
J. Anderson, A. van der Ziel, Symposium on Quantum 1/f Noise and its Implications, UM MEIS Center Conference Proceedings 1985

Shot Noise in Solid State Diodes
A. van der Ziel, J.B. Anderson, et al., SOLID STATE ELECTRONICS Vol. 29 No. 10 pp. 1069-1071 1986

Review of the Status of '1/f' Noise in 'n+-p' HgCdTe PhotoDetectors and other Devices
A. van der Ziel, P.H. Handel, X.L. Wu, J.B. Anderson, JOURNAL OF VACUUM SCIENCE AND TECHNOLOGY Vol. 4 No. 4 July/August 1986

Diffusion and Recombination '1/f' Noise in Long 'n+-p' HgCdTe Diodes
X. Wu, J.B. Anderson, A. van der Ziel, IEEE TRANS. ON ELECTRON DEVICES Vol. ED-34 No. 9 Sept. 1987

Classical '1/f' Diffusion Noise Spectrum for an 'n+-p' Diode of Arbitrary Length
J.B. Anderson, A. van der Ziel, Symposium on Low-Frequency Noise in Electronic Devices Including Quantum '1/f' Noise, UM MEIS Center Conference Proceedings 1988

Investigation of Cryogenic Charge Sensitive Amplifier Structures for Improved Spectrometer Bandwidth and Noise Performance
J. Anderson; J. Howard; 1994 Symposium on Radiation Measurements and Applications, May 16 1994 Univ. of Michigan